Eric Lai 7f1e9dbf3a soc/intel/cannonlake/acpi: Add board level s0ix call back ... Add board level s0ix call back. Since some driver doesn't care _ON/_OFF method. Add a control method for s0ix usage. BUG=b:129177593 TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I404f388b19355ae89b36d1fb07f9fb4f97eb3b2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/32539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>		2019-05-06 10:34:35 +00:00
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acpi
arch	arch/x86/acpi: Update VT-d DMA remapping structure flags setting	2019-05-01 18:33:55 +00:00
commonlib	src: include <assert.h> when appropriate	2019-04-23 10:01:36 +00:00
console	Fix code that would trip -Wtype-limits	2019-05-06 10:32:15 +00:00
cpu	cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE	2019-04-25 15:56:28 +00:00
device	x86emu: add console.h header to fix compilation	2019-05-02 05:00:33 +00:00
drivers	Fix code that would trip -Wtype-limits	2019-05-06 10:32:15 +00:00
ec	ec/google/wilco: Support board_id with EC provided ID	2019-04-18 23:43:06 +00:00
include	soc/skylake: Add missing PCH IDs	2019-05-06 10:29:02 +00:00
lib	vboot: refactor OPROM code	2019-04-30 21:47:25 +00:00
mainboard	Fix code that would trip -Wtype-limits	2019-05-06 10:32:15 +00:00
northbridge	nb/intel/haswell: correct a typo in Kconfig	2019-05-03 14:32:06 +00:00
security	vboot: refactor OPROM code	2019-04-30 21:47:25 +00:00
soc	soc/intel/cannonlake/acpi: Add board level s0ix call back	2019-05-06 10:34:35 +00:00
southbridge	Fix code that would trip -Wtype-limits	2019-05-06 10:32:15 +00:00
superio	superio/fintek/f71808a: Add more optional ramstage registers	2019-05-01 00:09:57 +00:00
vendorcode	Fix code that would trip -Wtype-limits	2019-05-06 10:32:15 +00:00
Kconfig	spd_bin: Do not depend CONFIG_DIMM_MAX on CONFIG_GENERIC_SPD_BIN	2019-05-06 10:31:38 +00:00