640a41f3ee
This commit adds an assertion to ensure that the values of
pmc_/gpe0_dw0, pmc_/gpe0_dw1, and pmc_/gpe0_dw2 in the
soc_intel_<soc>_config structure are unique.
This check helps to catch potential configuration errors early on,
preventing unexpected behavior during system initialization.
TEST=Built and booted normally. No assertion failure observed.
Able to catch the hidden issue due to overlapping Tier 1 GPE
configuration.
[DEBUG] CPU: Intel(R) Core(TM) 3 N355
[DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 0000001a
[DEBUG] CPU: AES supported, TXT supported, VT supported
...
...
[DEBUG] MCH: device id 4617 (rev 00) is Alderlake-N
[DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU
[DEBUG] IGD: device id 46d3 (rev 00) is Twinlake GT1
[EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/pmutil.c',
line 163
Change-Id: I6b4f2f90a858b9ec85145bce0542f1ce61d080be
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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| .. | ||
| amd | ||
| cavium | ||
| example/min86 | ||
| ibm/power9 | ||
| intel | ||
| mediatek | ||
| nvidia | ||
| qualcomm | ||
| rockchip | ||
| samsung | ||
| sifive | ||
| ti | ||
| ucb/riscv | ||