coreboot/src/include/cpu
Patrick Rudolph fd2cdf206d cpu/intel/smm/gen1: Optimize cpu_has_alternative_smrr
For most targets it's known if the CPU supports alternative SMRR
registers or not. Only on model_6fx runtime detection is necessary.

On all platforms this allows the compiler to optimize the code and
thus shrink the code size if alternative SMRR aren't supported.

TEST=On Lenovo X220 the ramstage is 308 bytes smaller.

Change-Id: I3a965d142f79ad587b8cedc9b4646b05e2a45f8b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91014
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2026-02-24 16:19:14 +00:00
..
amd treewide: Fix include guards 2025-11-13 14:58:40 +00:00
intel cpu/intel/smm/gen1: Optimize cpu_has_alternative_smrr 2026-02-24 16:19:14 +00:00
power src/cpu/power9: move part of scom.h to scom.c 2023-04-18 13:05:56 +00:00
x86 soc/intel/common/block/smm: Keep selected wake sources enabled in S5 2026-01-29 08:59:32 +00:00
cpu.h x86: Separate CPU and SoC physical address size 2023-12-22 12:26:59 +00:00