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Add documentation for the Intel PCH Top Swap based A/B redundancy mechanism. Describe the BOOTBLOCK and TOPSWAP bootblock regions, COREBOOT and COREBOOT_TS CBFS regions, the attempt_slot_b CMOS option and its application time, and how the active CBFS region is selected based on the Top Swap state. This follows the A/B redundancy proposal discussed on the coreboot mailing list: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/ Change-Id: I1b88989201e209b2f69964c067c432ff82a0057e Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90412 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
620 B
620 B
Intel SOC-specific documentation
This section contains documentation about coreboot on specific Intel SOCs.
Platforms
:maxdepth: 1
Common code development strategy <code_development_model/code_development_model.md>
FSP <fsp/index.md>
Broadwell <broadwell/index.md>
MP Initialization <mp_init/mp_init.md>
Microcode Updates <microcode.md>
Firmware Interface Table <fit.md>
Apollolake <apollolake/index.md>
CSE FW Update <cse_fw_update/cse_fw_update.md>
Xeon Scalable processor <xeon_sp/index.md>
Skylake/Kaby Lake BootGuard bypass <deguard.md>
Intel Top Swap based A/B redundancy <redundancy.md>