Aaron Durbin 7b58eedc10 baytrail: print dram configuration ... After running the MRC blob print out some information on the training: MRC version, number channels, DDR3 type, and DRAM frequency. Example output: MRC v0.90 2 channels of DDR3 @ 1066MHz Apparently there are two dunit IOSF ports -- 1 for each channel. However, certain registers really on live in channel 0. Thus, there was some changes to dunit support in the iosf area. BUG=chrome-os-partner:22875 BRANCH=None TEST=Built and booted bayleybay in different configs. Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172770 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>		2013-10-15 23:36:42 +00:00
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arch	x86: add common definitions for control registers	2013-10-10 20:48:43 +00:00
console	ARM: Generalize armv7 as arm.	2013-10-02 09:18:44 +00:00
cpu	coreboot: config to cache ramstage outside CBMEM	2013-10-11 23:27:01 +00:00
device	ARM: Generalize armv7 as arm.	2013-10-02 09:18:44 +00:00
drivers	drivers/gma: remove unused code	2013-10-11 20:36:54 +00:00
ec	chromeec: Implement full battery workaround at 6%	2013-09-16 23:31:17 +00:00
include	coreboot: config to cache ramstage outside CBMEM	2013-10-11 23:27:01 +00:00
lib	coreboot: config to cache ramstage outside CBMEM	2013-10-11 23:27:01 +00:00
mainboard	beltino: Configure PCIe bridges	2013-10-11 21:53:35 +00:00
northbridge	PEPPY, Haswell: refactor and create set_translation_table function in haswell/gma.c	2013-10-01 17:56:28 +00:00
soc	baytrail: print dram configuration	2013-10-15 23:36:42 +00:00
southbridge	lynxpoint: Export pch_enable_lpc() for SuperIO systems	2013-10-11 03:57:57 +00:00
superio	Drop prototype guarding for romcc	2013-05-10 11:55:20 -07:00
vendorcode	vboot: provide empty vboot_verify_firmware()	2013-10-15 22:27:27 +00:00
Kconfig	coreboot: config to cache ramstage outside CBMEM	2013-10-11 23:27:01 +00:00