Jonathan Neuschäfer 7b37a08b82 arch/riscv: Remove I/O space access functions (outb, etc.) ... RISC-V does not have the kind of I/O space that x86 has. Other architectures tend to leave out these definitions as well. Change-Id: I7328dae1f1fa4ef8772750244a0b11a3fa5aa88f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>		2018-04-11 09:30:08 +00:00
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include	arch/riscv: Remove I/O space access functions (outb, etc.)	2018-04-11 09:30:08 +00:00
boot.c	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
bootblock.S	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
id.ld	arch/riscv: Add missing license headers	2016-01-18 02:14:03 +01:00
id.S	src/arch/riscv/id.S: Don't hardcode the strings	2016-08-04 17:17:38 +02:00
Kconfig	arch/riscv: Make RVC support configurable	2018-02-20 20:44:53 +00:00
Makefile.inc	arch/riscv: Make RVC support configurable	2018-02-20 20:44:53 +00:00
mcall.c	arch/riscv: Remove the current SBI implementation	2017-12-02 05:24:32 +00:00
misc.c	arch/riscv: Add missing license headers	2016-01-18 02:14:03 +01:00
payload.S	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
prologue.inc	tree: drop last paragraph of GPL copyright header	2015-10-31 21:37:39 +01:00
stages.c	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
tables.c	lib: add common write_tables() implementation	2016-04-21 20:49:05 +02:00
trap_handler.c	arch/riscv: Update encoding.h and adjust related code	2018-02-20 20:46:39 +00:00
trap_util.S	arch/riscv: Align trap_entry to 4 bytes, as required by spec	2018-02-20 20:44:43 +00:00
virtual_memory.c	arch/riscv: Delegate the page fault exceptions	2018-02-20 20:46:53 +00:00