arch/riscv: Make RVC support configurable

In order to support RISC-V processors with and without the RVC
extension, configure the architecture variant (-march=...) explicitly.

NOTE: Spike does support RVC, but currently doesn't select
      ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't
      support RVC.

Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/arch/riscv/Kconfig

@@ -2,6 +2,13 @@ config ARCH_RISCV
 	bool
 	default n
 
+config ARCH_RISCV_COMPRESSED
+	bool
+	default n
+	help
+	  Enable this option if your RISC-V processor supports compressed
+	  instructions (RVC). Currently, this enables RVC for all stages.
+
 config ARCH_BOOTBLOCK_RISCV
 	bool
 	default n

src/arch/riscv/Makefile.inc

@@ -15,14 +15,24 @@
 ##
 ################################################################################
 
-riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany
-
-riscv_asm_flags =
+################################################################################
+## RISC-V specific options
+################################################################################
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
 check-ramstage-overlap-regions += stack
 endif
 
+riscv_arch = rv64imafd
+
+ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y)
+	riscv_arch := $(riscv_arch)c
+endif
+
+riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch)
+
+riscv_asm_flags = -march=$(riscv_arch)
+
 ################################################################################
 ## bootblock
 ################################################################################