7436c59875
Add register tables and device IDs for Phoenix AM5 desktop CPUs. TEST=Dump all data with amdtool on MSI PRO B650M-A. Change-Id: Ia7af9194fb7516e98b7cddee2bfc65af12d56dc0 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90009 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
424 lines
11 KiB
C
424 lines
11 KiB
C
/* amdtool - dump all registers on an AMD CPU + chipset based system */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdio.h>
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#include <stdlib.h>
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#include "amdtool.h"
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#include "smn.h"
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#define AMD_FCH_SPIBAR_OFFSET 0xa0
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#define SPI_SMN_BASE 0x2DC4000
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static const io_register_t spi100_speed_cfg_fields[] = {
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{ 0x0, 4, "TPM Speed" },
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{ 0x4, 4, "Alt Speed" },
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{ 0x8, 4, "Fast Read Speed" },
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{ 0xc, 4, "Normal Speed" },
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};
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static const io_register_t spi100_host_prefetch_cfg_fields[] = {
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{ 0x0, 7, "Host Prefetch Size" },
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{ 0x7, 1, "Host Prefetch on 64B Boudnary" },
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{ 0x8, 4, "Host Hit Range" },
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{ 0xc, 1, "Host Will Hit Enable" },
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{ 0xd, 1, "Host Hit Soon Enable" },
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{ 0xe, 1, "Host Burst Enable" },
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{ 0xf, 1, "Host Burst to 4DW Enable" },
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};
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static const io_register_t spi_cntl0_fields[] = {
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{ 0x0, 8, "Spi OpCode (Reserved)" },
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{ 0x8, 1, "Disable Index Retry" },
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{ 0x9, 1, "Index Cacheline Stop" },
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{ 0xA, 2, "ROM Protection Compare Range" },
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{ 0x12, 1, "SPI Read Mode [0]" },
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{ 0x15, 1, "Illegal Access" },
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{ 0x16, 1, "SPI MAC Access ROM Enable" },
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{ 0x17, 1, "SPI Host Access ROM Enable" },
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{ 0x1c, 1, "SPI Clock Gate" },
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{ 0x1d, 1, "SPI Read Mode [1]" },
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{ 0x1e, 1, "SPI Read Mode [2]" },
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{ 0x1f, 1, "SPI Busy" },
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};
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static const io_register_t kunlun_alt_spi_cs_fields[] = {
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{ 0x0, 2, "Alt SPI CS Enable" },
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{ 0x3, 1, "SPI Protect Enable 0" },
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{ 0x5, 1, "SPI Protect Lock" },
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{ 0x6, 1, "Lock SPI CS" },
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};
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static const io_register_t tacoma_alt_spi_cs_fields[] = {
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{ 0x0, 2, "Alt SPI CS Enable" },
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{ 0x3, 1, "SPI Protect Enable 0" },
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{ 0x5, 1, "SPI Protect Lock" },
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};
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static const char * const spi100_speed_values[] = {
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"66.66 MHz",
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"33.33 MHz",
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"22.22 MHz",
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"16.66 Mhz",
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"100 MHz",
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"800 KHz",
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"Defined in SPIx6C[5:0]",
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"Defined in SPIx6C[13:8]"
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};
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static const io_register_t spi_bar_registers[] = {
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{ 0x00, 4, "SPI Control 0" },
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{ 0x04, 4, "SPI Restricted Command" },
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{ 0x08, 4, "SPI Restricted Command 2" },
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{ 0x0C, 4, "SPI Control 1" },
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{ 0x10, 4, "ESPI Control" },
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{ 0x14, 4, "SPI Command Value 1" },
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{ 0x18, 4, "SPI Command Value 2" },
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{ 0x1C, 1, "ROMCP CS" },
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{ 0x1D, 1, "SPI ALT CS" },
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{ 0x20, 4, "SPI100 Enable" },
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{ 0x24, 4, "SPI100 Precyc0" },
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{ 0x28, 4, "SPI100 Precyc1" },
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{ 0x2C, 2, "SPI100 Host Prefetch Config" },
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{ 0x2E, 2, "TPM SPI DI Timeout" },
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{ 0x30, 2, "ROM2 Address Override" },
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{ 0x32, 2, "SPI100 Dummy Cycle Config" },
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{ 0x32, 2, "SPI100 Rx Timing Config" },
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{ 0x40, 1, "DDR Command Code" },
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{ 0x41, 1, "QDR Command Code" },
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{ 0x42, 1, "DPR Command Code" },
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{ 0x43, 1, "QPR Command Code" },
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{ 0x44, 1, "Mode Byte" },
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{ 0x50, 4, "Addr32 Control 0" },
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{ 0x54, 4, "Addr32 Control 1" },
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{ 0x58, 4, "Addr32 Control 2" },
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{ 0x5C, 4, "Addr32 Control 3" },
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{ 0x60, 4, "BAR 64MB ROM3 Low" },
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{ 0x64, 4, "BAR 64MB ROM3 High" },
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{ 0x68, 4, "SPI Restricted Command 3" },
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{ 0x6C, 4, "SPI Speed" },
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{ 0x70, 4, "Host Interrupt" },
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{ 0x74, 4, "LPC SPI Interrupt" },
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{ 0x78, 4, "Flash Idle COunt" },
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{ 0xFC, 2, "SPI Misc Control" },
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};
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int use_smn_access = 0;
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volatile uint8_t *spibar = NULL;
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uint32_t spi_smn_base = 0;
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static uint8_t spi_read8(uint32_t offset)
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{
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if (use_smn_access)
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return smn_read8(spi_smn_base + offset);
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else
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return read8(spibar + offset);
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}
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static uint16_t spi_read16(uint32_t offset)
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{
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if (use_smn_access)
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return smn_read16(spi_smn_base + offset);
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else
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return read16(spibar + offset);
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}
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static uint32_t spi_read32(uint32_t offset)
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{
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if (use_smn_access)
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return smn_read32(spi_smn_base + offset);
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else
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return read32(spibar + offset);
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}
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static int print_spi_cntrl0(struct pci_dev *sb)
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{
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int i, size = 0;
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int smbus_rev = 0;
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uint32_t spi_cntrl0 = UINT32_MAX;
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const io_register_t *spi_cntrl_register = NULL;
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printf("\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_AMD_FCH_LPC_2:
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smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
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if (smbus_rev == -1)
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return 1;
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switch (smbus_rev) {
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case 0x71:
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spi_cntrl0 = spi_read32(0);
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spi_cntrl_register = spi_cntl0_fields;
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size = ARRAY_SIZE(spi_cntl0_fields);
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break;
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default:
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printf("Error: Dumping SPI CNTRL on this southbridge is not (yet) supported.\n");
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return 1;
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}
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break;
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default:
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printf("Error: Dumping SPI CNTRL on this southbridge is not (yet) supported.\n");
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return 1;
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}
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printf("SPI_CNTRL0 = 0x%08x\n\n", spi_cntrl0);
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if (spi_cntrl_register) {
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for (i = 0; i < size; i++) {
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unsigned int val = spi_cntrl0 >> spi_cntrl_register[i].addr;
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val &= ((1 << spi_cntrl_register[i].size) -1);
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printf("0x%04x = %s\n", val, spi_cntrl_register[i].name);
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}
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}
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return 0;
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}
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static int print_spi_alt_cs(struct pci_dev *sb, struct pci_dev *nb)
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{
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int i, size = 0;
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int smbus_rev = 0;
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uint8_t spi_alt_cs = 0xff;
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const io_register_t *spi_alt_cs_register = NULL;
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printf("\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_AMD_FCH_LPC_2:
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smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
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if (smbus_rev == -1)
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return 1;
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switch (smbus_rev) {
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case 0x71:
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switch (nb->device_id) {
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case PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX:
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spi_alt_cs = spi_read8(0x1d);
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spi_alt_cs_register = kunlun_alt_spi_cs_fields;
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size = ARRAY_SIZE(kunlun_alt_spi_cs_fields);
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break;
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case PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX:
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spi_alt_cs = spi_read8(0x1d);
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spi_alt_cs_register = tacoma_alt_spi_cs_fields;
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size = ARRAY_SIZE(tacoma_alt_spi_cs_fields);
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break;
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default:
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goto alt_cs_err;
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}
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break;
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default:
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goto alt_cs_err;
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}
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break;
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default:
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goto alt_cs_err;
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}
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printf("SPI_ALT_CS = 0x%02x\n\n", spi_alt_cs);
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if (spi_alt_cs_register) {
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for (i = 0; i < size; i++) {
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unsigned int val = spi_alt_cs >> spi_alt_cs_register[i].addr;
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val &= ((1 << spi_alt_cs_register[i].size) -1);
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printf("0x%04x = %s\n", val, spi_alt_cs_register[i].name);
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}
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}
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return 0;
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alt_cs_err:
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printf("Error: Dumping SPI_ALT_CS on this southbridge is not (yet) supported.\n");
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return 1;
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}
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static int print_spi_speed_config(struct pci_dev *sb)
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{
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size_t i, size = 0, values_size = 0;
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uint16_t spi_speed_cfg = UINT16_MAX;
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const io_register_t *spi_speed_cfg_register = NULL;
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const char * const *speed_values = NULL;
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int smbus_rev = 0;
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printf("\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_AMD_FCH_LPC_2:
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smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
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if (smbus_rev == -1)
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return 1;
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switch (smbus_rev) {
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case 0x71:
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spi_speed_cfg = spi_read16(0x22);
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spi_speed_cfg_register = spi100_speed_cfg_fields;
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size = ARRAY_SIZE(spi100_speed_cfg_fields);
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speed_values = spi100_speed_values;
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values_size = ARRAY_SIZE(spi100_speed_values);
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break;
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default:
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printf("Error: Dumping SPI100_SPEED_CFG on this southbridge is not (yet) supported.\n");
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return 1;
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}
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break;
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default:
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printf("Error: Dumping SPI100_SPEED_CFG on this southbridge is not (yet) supported.\n");
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return 1;
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}
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printf("SPI100_SPEED_CFG = 0x%04x\n\n", spi_speed_cfg);
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if (spi_speed_cfg_register && speed_values) {
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for (i = 0; i < size; i++) {
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unsigned int val = spi_speed_cfg >> spi_speed_cfg_register[i].addr;
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val &= ((1 << spi_speed_cfg_register[i].size) -1);
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if (val < values_size)
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printf("0x%04x = %s (%s)\n", val, spi_speed_cfg_register[i].name,
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speed_values[val]);
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else
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printf("0x%04x = %s (Reserved)\n", val, spi_speed_cfg_register[i].name);
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}
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}
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return 0;
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}
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static int print_spi_host_prefetch(struct pci_dev *sb)
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{
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int i, size = 0;
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uint16_t spi_host_prefetch = UINT16_MAX;
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const io_register_t *spi_host_prefetch_register = NULL;
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int smbus_rev = 0;
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printf("\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_AMD_FCH_LPC_2:
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smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
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if (smbus_rev == -1)
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return 1;
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switch (smbus_rev) {
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case 0x71:
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spi_host_prefetch = spi_read16(0x2c);
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spi_host_prefetch_register = spi100_host_prefetch_cfg_fields;
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size = ARRAY_SIZE(spi100_host_prefetch_cfg_fields);
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break;
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default:
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printf("Error: Dumping SPI100_HOST_PREFETCH_CFG on this southbridge is not (yet) supported.\n");
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return 1;
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}
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break;
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default:
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printf("Error: Dumping SPI100_HOST_PREFETCH_CFG on this southbridge is not (yet) supported.\n");
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return 1;
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}
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printf("SPI100_HOST_PREFETCH_CFG = 0x%04x\n\n", spi_host_prefetch);
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if (spi_host_prefetch_register) {
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for (i = 0; i < size; i++) {
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unsigned int val = spi_host_prefetch >> spi_host_prefetch_register[i].addr;
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val &= ((1 << spi_host_prefetch_register[i].size) - 1);
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printf("0x%04x = %s\n", val, spi_host_prefetch_register[i].name);
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}
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}
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return 0;
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}
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static int print_spibar(struct pci_dev *sb, struct pci_dev *nb)
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{
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int i, size = 0, spi_size = 0x1000;
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uint32_t spibar_phys, spibar_mask;
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const io_register_t *spi_register = NULL;
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int smbus_rev;
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printf("\n============= SPI Bar ==============\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_AMD_FCH_LPC_2:
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smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
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if (smbus_rev == -1)
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return 1;
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switch (smbus_rev) {
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case 0x71:
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size = ARRAY_SIZE(spi_bar_registers);
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spi_register = spi_bar_registers;
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spibar_mask = 0xffffff00;
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spi_smn_base = SPI_SMN_BASE;
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break;
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default:
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printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
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return 1;
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}
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break;
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default:
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printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
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return 1;
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}
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spibar_phys = pci_read_long(sb, AMD_FCH_SPIBAR_OFFSET);
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if ((spibar_phys & spibar_mask) == 0 || (spibar_phys == 0xffffffff)) {
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if (spi_smn_base != 0) {
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use_smn_access = 1;
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} else {
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perror("Error SPIBAR not programmed");
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return 1;
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}
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} else {
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if (spibar_phys == UINT32_MAX) {
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perror("Error SPIBAR invalid");
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return 1;
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}
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spibar = map_physical(spibar_phys & spibar_mask, spi_size);
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if (spibar == NULL) {
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perror("Error mapping SPIBAR");
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return 1;
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}
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}
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for (i = 0; i < size; i++) {
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switch(spi_register[i].size) {
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case 1:
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printf("0x%08x = %s\n", spi_read8(spi_register[i].addr), spi_register[i].name);
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break;
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case 2:
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printf("0x%08x = %s\n", spi_read16(spi_register[i].addr), spi_register[i].name);
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break;
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case 4:
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printf("0x%08x = %s\n", spi_read32(spi_register[i].addr), spi_register[i].name);
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break;
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case 8:
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printf("0x%08x%08x = %s\n", spi_read32(spi_register[i].addr + 4),
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spi_read32(spi_register[i].addr), spi_register[i].name);
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break;
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}
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}
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print_spi_cntrl0(sb);
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print_spi_alt_cs(sb, nb);
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print_spi_speed_config(sb);
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print_spi_host_prefetch(sb);
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if (spibar)
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unmap_physical((void *)spibar, spi_size);
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printf("\n====================================\n");
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return 0;
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}
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int print_spi(struct pci_dev *sb, struct pci_dev *nb)
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{
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return print_spibar(sb, nb);
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}
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