Ritul Guru 75a073d5ff soc/amd/phoenix: update mmconf base address and size ... 0xF8000000 was taken from old platform during phoenix porting, updating it to 0xE0000000 to make room for 256 pci busses which is required for usb4 and hotplug support. mmconf size gets set to 0x10000000 when 256 busses are used. Change-Id: Ic143171f5650aff5db48c8f477d7aca3e7f5c1e7 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71870 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2023-01-13 23:42:04 +00:00
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cezanne	soc/amd/cezanne: use common SMU S3/4/5 entry message code	2023-01-13 23:36:03 +00:00
common	soc/amd: introduce common SMU S3/4/5 entry message code	2023-01-13 23:35:48 +00:00
glinda	soc/amd/glinda: use common SMU S3/4/5 entry message code	2023-01-13 23:36:46 +00:00
mendocino	soc/amd/mendocino: use common SMU S3/4/5 entry message code	2023-01-13 23:36:22 +00:00
phoenix	soc/amd/phoenix: update mmconf base address and size	2023-01-13 23:42:04 +00:00
picasso	soc/amd/picasso: use common SMU S3/4/5 entry message code	2023-01-13 23:35:56 +00:00
stoneyridge	treewide: Remove unused <cpu/amd/mtrr.h>	2023-01-12 05:07:21 +00:00