coreboot/src/soc/amd
Patrick Rudolph 72ed0426d8 soc/amd/*/acpi: Define PCI bridges in DSDT
Add all known PCI bridge devices to the DSDT. This allows to reference
the devices from DSDT, allowing to add more SoC DSDT code and it allows
mainboard developers to add board specific ACPI code for devices behind
PCIe bridges (like NVMe D3cold).

Currently this is only possible using SSDT generators. The SSDT ACPI
generation is also broken, since the mainboard SSDT is run before SoC
SSDT, causing the interpreter to complain about missing devices.

TEST=Still boots on amd/birman_plus. No ACPI errors seen in dmesg.

Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I9d6f84b97fa943bb531d6b7b3f16c0422cd7901f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89456
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2026-02-05 11:37:52 +00:00
..
cezanne soc/amd/*/acpi: Define PCI bridges in DSDT 2026-02-05 11:37:52 +00:00
common soc/amd/*/acpi: Define PCI bridges in DSDT 2026-02-05 11:37:52 +00:00
genoa_poc soc/amd: add ACPI code for I3C controller 2025-12-01 19:41:52 +00:00
glinda soc/amd/*/acpi: Define PCI bridges in DSDT 2026-02-05 11:37:52 +00:00
mendocino soc/amd/*/acpi: Define PCI bridges in DSDT 2026-02-05 11:37:52 +00:00
phoenix soc/amd/*/acpi: Define PCI bridges in DSDT 2026-02-05 11:37:52 +00:00
picasso soc/amd/*/acpi: Define PCI bridges in DSDT 2026-02-05 11:37:52 +00:00
stoneyridge soc/amd/stoneyridge: Generate SATA ACPI registers at runtime 2025-11-14 16:28:19 +00:00
turin_poc vendorcode/amd/opensil: Add Turin OpenSIL 2026-01-28 13:32:33 +00:00