coreboot/src/mainboard/emulation
Krystian Hebel 44ec090551 ppc64: Kconfig switch for bootblock in SEEPROM, zero HRMOR
On PPC64 each address is logically OR'ed with HRMOR (Hypervisor Real
Mode Offset Register) before it is dispatched to the underlying memory,
meaning that memory space overlaps at the least significant bit set in
HRMOR. coreboot is entered with HRMOR = 4GB-128MB both on hardware
(when started by hostboot bootloader) and in Qemu in hb-mode. This means
that memory overlaps every 128MB in this particular case. HRMOR can be
explicitly ignored when MSB of an address is set, but this would require
using different memory model for linking.

If we zero HRMOR in bootblock, linking can be done against real address.
This greatly simplifies memory layout and allows to forget about HRMOR
from that point on.

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Change-Id: I0170463968c91b943c4b0dc15fe73fa616a164da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67067
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-08-28 20:13:51 +00:00
..
qemu-aarch64 soc/amd/common/psp_verstage: Remove arch/io.h 2025-04-02 16:03:34 +00:00
qemu-armv7
qemu-i440fx mb/*/*/*.fmd: Start flash at 0 2025-04-09 17:11:43 +00:00
qemu-power8 ppc64: Kconfig switch for bootblock in SEEPROM, zero HRMOR 2025-08-28 20:13:51 +00:00
qemu-power9 ppc64: Kconfig switch for bootblock in SEEPROM, zero HRMOR 2025-08-28 20:13:51 +00:00
qemu-q35 mb/*/*/*.fmd: Start flash at 0 2025-04-09 17:11:43 +00:00
qemu-riscv mb/qemu-riscv: set PCI_IOBASE 2025-08-28 20:10:19 +00:00
qemu-sbsa tree: remove duplicated includes 2025-04-20 05:13:57 +00:00
spike-riscv
Kconfig
Kconfig.name