Arthur Heymans 1410224cf4 soc/intel/xeon_sp: Use common cpu/intel romstage entry ... This removes some boilerplate like starting the console and also adds a "start of romstage" timestamp. Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2020-11-05 00:02:07 +00:00
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amd	soc/amd/common/psp: move v1-only mailbox commands to separate section	2020-11-04 19:37:42 +00:00
cavium	soc/cavium: Drop unneeded empty lines	2020-09-22 17:14:49 +00:00
example	x86: Add a minimal example SoC along with a board	2020-10-30 21:34:18 +00:00
intel	soc/intel/xeon_sp: Use common cpu/intel romstage entry	2020-11-05 00:02:07 +00:00
mediatek	soc/mediatek/mt8192: Do dram full calibration	2020-10-29 00:30:34 +00:00
nvidia	soc/nvidia: Drop unneeded empty lines	2020-09-22 17:14:59 +00:00
qualcomm	sc7180: Fix prefill requirement and correct the fetch start check	2020-11-02 22:04:33 +00:00
rockchip	soc/rockchip/rk3288/include/soc/display.h: Add missing includes	2020-10-19 07:12:07 +00:00
samsung	src/soc/samsung: Move common headers to "common/include/soc"	2020-10-19 07:11:32 +00:00
sifive	include/console/uart: make index parameter unsigned	2020-09-12 14:59:33 +00:00
ti	include/console/uart: make index parameter unsigned	2020-09-12 14:59:33 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00