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Subrata Banik 7029665482 mb/intel/adlrvp: Add support for DDR5 memory 
This patch adds DDR5 memory configuration parameters to FSP.

TEST=Able to build and boot ADLRVP with DDR5 memory.

Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05 07:29:44 +00:00
..
acpi soc/intel/skl,acpi/acpigen: convert global CPPC package to local one 2020-11-04 09:40:21 +00:00
arch arch/x86/smbios: Populate SMBIOS type 7 with cache information 2020-10-26 06:54:04 +00:00
commonlib lib/libpayload: Replace strapping_ids with new board configuration entry 2020-10-30 15:25:28 +00:00
console console/init: Drop CONSOLE_LEVEL_CONST 2020-10-26 06:48:45 +00:00
cpu cpu/intel/haswell: Move smmrelocate.c MSR definitions to header 2020-11-03 19:12:01 +00:00
device azalia: Treat all negative return values as errors 2020-11-02 10:41:15 +00:00
drivers soc/intel/common: Create common Intel FSP reset code block 2020-11-02 10:43:40 +00:00
ec ec/purism/librem: Convert to ASL 2.0 syntax 2020-11-04 09:44:11 +00:00
include acpi/acpi.h: Update region spaces 2020-11-04 09:40:40 +00:00
lib lib/libpayload: Replace strapping_ids with new board configuration entry 2020-10-30 15:25:28 +00:00
mainboard mb/intel/adlrvp: Add support for DDR5 memory 2020-11-05 07:29:44 +00:00
northbridge haswell: Add Intel TXT support in romstage 2020-11-04 23:53:51 +00:00
security haswell: Add Intel TXT support in romstage 2020-11-04 23:53:51 +00:00
soc soc/intel/xeon_sp: Use common cpu/intel romstage entry 2020-11-05 00:02:07 +00:00
southbridge sb/intel/lynxpoint/acpi/gpio.asl: Simplify constants 2020-11-04 23:22:04 +00:00
superio superio/nuvoton: Factor out equivalent Kconfig option 2020-10-19 07:06:20 +00:00
vendorcode vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425 2020-11-02 04:43:39 +00:00
Kconfig soc/intel/xeon_sp: Move function debug macros 2020-10-29 16:44:19 +00:00