coreboot/src
Kein Yuan 6dbcc677ce Baytrail/dptf: Always return 0 in TCPU._PPC
According to DPTF team _PPC in TCPU must return 0 always.

BUG=chromium:355964
TEST=Pass build.
BRANCH=rambi

Change-Id: I76f0da27757ba4717f0e392bcd80e890d925061a
Original-Change-Id: I8b9e17e5479e8a226cb11cd43ce888a3e4dead73
Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/193069
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
2014-04-04 20:27:30 +00:00
..
arch arm: allow vboot rmodule to be included in cbfs 2014-04-03 22:39:06 +00:00
console console: Make cbmem depend on x86. 2014-03-22 06:24:02 +00:00
cpu spi: Remove unused parameters from spi_flash_probe and setup_spi_slave. 2014-04-01 23:21:22 +00:00
device Remove stale char[] initialization causing unaligned memory access 2014-03-14 03:44:47 +00:00
drivers vboot: allow for non-memory-mapped VBOOT regions 2014-04-03 22:35:56 +00:00
ec spi: Change spi_xfer to work in units of bytes instead of bits. 2014-04-02 04:25:16 +00:00
include spi: Change spi_xfer to work in units of bytes instead of bits. 2014-04-02 04:25:16 +00:00
lib edid: Fix source indent. 2014-04-04 04:54:46 +00:00
mainboard Big, Blaze: Set I2S1 Source to CLK_M to Fix Beep 2014-04-01 02:49:39 +00:00
northbridge spi: Remove unused parameters from spi_flash_probe and setup_spi_slave. 2014-04-01 23:21:22 +00:00
soc Baytrail/dptf: Always return 0 in TCPU._PPC 2014-04-04 20:27:30 +00:00
southbridge spi: Change spi_xfer to work in units of bytes instead of bits. 2014-04-02 04:25:16 +00:00
superio pnp: Allow setting of misc register 0xf4 in device tree 2013-12-20 00:37:38 +00:00
vendorcode tegra124: Skip display init when vboot says we don't need it. 2014-04-03 22:41:54 +00:00
Kconfig armv8: add support for armv8 cpu 2014-01-07 02:48:47 +00:00