ae68ef3684
The PCODE mailbox is primarily used by CPU code in ramstage. However, it is also used as part of enabling DDR 2x refresh rate, which is now implemented in coreboot as part of NRI (native RAM init). The PCODE mailbox functions in CPU code were not exported at the time NRI was being developed, so I chose to temporarily copy the functions into NRI code to make it easier to rebase NRI patches since it avoids potential merge conflicts. After a few years of rebasing patches, NRI finally got submitted, so there's no reason to keep duplicate code in the tree anymore. Put the relevant PCODE functions into a new file, which gets compiled for both ramstage (CPU init) and romstage (NRI). The BCLK calibration function is only used in ramstage so there's no need to move it. Change-Id: I340625fabc072139b8def254f1ce6b19f360adcd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> |
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| intel | ||
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| qemu-x86 | ||
| via | ||
| x86 | ||
| Kconfig | ||
| Makefile.mk | ||