coreboot/src/cpu
Patrick Rudolph b4b9e87669 cpu/intel/model_206xx: Load microcode in pre_mp_init()
Ensure that BSP has latest microcode loaded before MPinit starts.
This aligns the code with other platforms ensuring that the microcode
on the BSP is up to date.

It likely has updated microcode before enabling NEM, so this is a
nop, but it also ensures that the microcode is located in CBFS
before the MTRRs are setup using x86_setup_mtrrs_with_detect() which
removes caching the SPI flash MMIO area.

Since intel_microcode_find() caches the microcode location
get_microcode_info() will be faster since it doesn't need to access
the CBFS.

TEST=Lenovo X220 still boots.

Change-Id: Ic4c5d1a06ce314b38b92e8a9c089ed901716ff27
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90893
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2026-02-11 10:02:35 +00:00
..
amd treewide: Remove unused CHIPs 2024-02-20 11:01:36 +00:00
armltd arch to cpu: Add SPDX license headers to Kconfig files 2024-02-18 01:58:52 +00:00
intel cpu/intel/model_206xx: Load microcode in pre_mp_init() 2026-02-11 10:02:35 +00:00
power9 include/device/device.h: Remove CHIP_NAME() macro 2024-01-31 09:51:58 +00:00
qemu-power8 include/device/device.h: Remove CHIP_NAME() macro 2024-01-31 09:51:58 +00:00
qemu-x86 cpu/qemu: Enable IDT_IN_EVERY_STAGE 2024-12-17 17:37:54 +00:00
via cpu/via/c7: Compress ramstage with LZ4 by default 2024-11-21 09:26:17 +00:00
x86 x86/mtrr: Avoid WC for VGA BARs above 4GiB 2026-02-07 20:32:47 +00:00
Kconfig arch to cpu: Add SPDX license headers to Kconfig files 2024-02-18 01:58:52 +00:00
Makefile.mk Revert "src/cpu,soc/amd/common/block/cpu: Add preload_microcode" 2025-04-14 13:55:47 +00:00