Jonathan Neuschäfer 5135f1184d RISC-V boards: Remove PAGETABLES section from memlayout.ld ... RISC-V doesn't set up page tables anymore, since commit b26759d703 ("arch/riscv: Don't set up virtual memory"). Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2018-04-27 09:07:43 +00:00
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include	RISC-V boards: Remove PAGETABLES section from memlayout.ld	2018-04-27 09:07:43 +00:00
boot.c	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
bootblock.S	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
id.ld	arch/riscv: Add missing license headers	2016-01-18 02:14:03 +01:00
id.S	src/arch/riscv/id.S: Don't hardcode the strings	2016-08-04 17:17:38 +02:00
Kconfig	arch/riscv: Make RVC support configurable	2018-02-20 20:44:53 +00:00
Makefile.inc	arch/riscv: Make RVC support configurable	2018-02-20 20:44:53 +00:00
mcall.c	arch/riscv: Remove the current SBI implementation	2017-12-02 05:24:32 +00:00
misc.c	arch/riscv: Add missing license headers	2016-01-18 02:14:03 +01:00
payload.S	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
prologue.inc
stages.c	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
tables.c	lib: add common write_tables() implementation	2016-04-21 20:49:05 +02:00
trap_handler.c	arch/riscv: Update encoding.h and adjust related code	2018-02-20 20:46:39 +00:00
trap_util.S	arch/riscv: Align trap_entry to 4 bytes, as required by spec	2018-02-20 20:44:43 +00:00
virtual_memory.c	arch/riscv: Delegate the page fault exceptions	2018-02-20 20:46:53 +00:00