7436c59875
Add register tables and device IDs for Phoenix AM5 desktop CPUs. TEST=Dump all data with amdtool on MSI PRO B650M-A. Change-Id: Ia7af9194fb7516e98b7cddee2bfc65af12d56dc0 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90009 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
126 lines
3 KiB
C
126 lines
3 KiB
C
/* amdtool - dump all registers on an AMD CPU + chipset based system */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdio.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include <commonlib/helpers.h>
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#include "amdtool.h"
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static const io_register_t lpc_cfg_registers[] = {
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{0x00, 4, "ID"},
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{0x04, 2, "CMD"},
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{0x06, 2, "STS"},
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{0x08, 1, "RID"},
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{0x09, 1, "CC[2]"},
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{0x0A, 1, "CC[1]"},
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{0x0B, 1, "CC[0]"},
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{0x0C, 1, "CLSIZE"},
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{0x0D, 1, "LATTMR"},
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{0x0E, 1, "HTYPE"},
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{0x2C, 4, "SS"},
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{0x34, 1, "CAPP"},
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{0x40, 1, "PCICTL"},
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{0x44, 4, "IOPDE"},
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{0x48, 4, "IOMPDE"},
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{0x4C, 4, "MEMRNG"},
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{0x50, 4, "ROMPROT[0]"},
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{0x54, 4, "ROMPROT[1]"},
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{0x58, 4, "ROMPROT[2]"},
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{0x5C, 4, "ROMPROT[3]"},
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{0x60, 2, "LPCMEMADDRSTART"},
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{0x62, 2, "LPCMEMADDREND"},
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{0x64, 2, "PCIWIDEIO[0]"},
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{0x66, 2, "PCIWIDEIO[1]"},
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{0x68, 2, "ROMADDRSTART[0]"},
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{0x6A, 2, "ROMADDREND[0]"},
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{0x6C, 2, "ROMADDRSTART[1]"},
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{0x6E, 2, "ROMADDREND[1]"},
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{0x70, 4, "FWHUBSEL"},
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{0x74, 4, "ALTWIDEIO"},
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{0x78, 4, "MISCCTL"},
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{0x7C, 1, "TPM"},
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{0x7D, 1, "LPCCLKCNTL"},
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{0x84, 4, "TMKBCBASELO"},
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{0x88, 4, "TMKBCBASEHI"},
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{0x8C, 2, "TMKBCREMAP"},
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{0x90, 2, "PCIWIDEIO[2]"},
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{0x98, 4, "EC_LPC_CTL"},
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{0x9C, 4, "GEC_SHDWROM_ADDR"},
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{0xA0, 4, "SPIBASE"},
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{0xA4, 2, "EC_PORT_ADDR"},
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{0xA8, 4, "ROM3_LO"},
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{0xAC, 4, "ROM3_HI"},
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{0xB8, 4, "ROMDMACTL"},
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{0xBA, 1, "EC_CTL"},
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{0xBB, 1, "HOST_CTL"},
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{0xC8, 4, "CLIENT_ROM_PROTECT"},
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{0xCC, 4, "AUTO_ROM_CFG"},
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{0xD0, 4, "CLKCTL"},
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{0xD4, 4, "CLKRUNOPT"},
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{0xDC, 4, "MISCCTL"},
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{0xE0, 4, "ROMPROT[4]"},
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{0xE4, 4, "ROMPROT[5]"},
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{0xE8, 4, "ROMPROT[6]"},
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{0xEC, 4, "ROMPROT[7]"},
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};
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int print_lpc(struct pci_dev *sb)
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{
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size_t i, cfg_registers_size = 0;
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const io_register_t *cfg_registers;
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int smbus_rev = 0;
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printf("\n========== LPC =========\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_AMD_FCH_LPC_2:
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smbus_rev = find_smbus_dev_rev(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_2);
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if (smbus_rev == -1)
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return 1;
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switch (smbus_rev) {
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case 0x71:
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cfg_registers = lpc_cfg_registers;
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cfg_registers_size = ARRAY_SIZE(lpc_cfg_registers);
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break;
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default:
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printf("Error: Dumping LPC on this southbridge is not (yet) supported.\n");
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return 1;
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}
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break;
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default:
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printf("Error: Dumping LPC on this southbridge is not (yet) supported.\n");
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return 1;
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}
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for (i = 0; i < cfg_registers_size; i++) {
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switch (cfg_registers[i].size) {
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case 4:
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printf("0x%04x: 0x%08x (%s)\n",
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cfg_registers[i].addr,
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pci_read_long(sb, cfg_registers[i].addr),
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cfg_registers[i].name);
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break;
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case 2:
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printf("0x%04x: 0x%04x (%s)\n",
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cfg_registers[i].addr,
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pci_read_word(sb, cfg_registers[i].addr),
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cfg_registers[i].name);
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break;
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case 1:
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printf("0x%04x: 0x%02x (%s)\n",
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cfg_registers[i].addr,
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pci_read_byte(sb, cfg_registers[i].addr),
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cfg_registers[i].name);
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break;
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default:
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printf("Error: register size %d not implemented.\n",
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cfg_registers[i].size);
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break;
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}
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}
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return 0;
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}
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