coreboot/src
David Hendricks 5b9598b74c exynos5420: add I2C8-10 to clock_get_periph_rate()
This adds entries for I2C8-10 to giant switch statement in
clock_get_periph_rate(). It also eliminates the I2C peripheral's
usage of clk_bit_info since it's confusing and error-prone.

BUG=chrome-os-partner:19420
BRANCH=none
TEST=TODO...

Change-Id: I4b006c034575e6bd1f4722503668b9a142020eb5
Reviewed-on: https://gerrit.chromium.org/gerrit/58782
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
2013-06-17 23:34:20 -07:00
..
arch armv7a: Enable native memcpy / memset 2013-06-17 18:35:45 -07:00
console ARM: Separate the early console (romstage) from the bootblock console. 2013-06-13 21:15:40 -07:00
cpu exynos5420: add I2C8-10 to clock_get_periph_rate() 2013-06-17 23:34:20 -07:00
device Clean up POST codes for Boot State machine 2013-06-10 18:08:24 -07:00
drivers elog: Get rid of the descriptor type and some unnecessary wrappers. 2013-06-14 16:15:36 -07:00
ec ec: Reserve correct ioport regions for Chrome OS EC to use 2013-06-12 14:02:10 -07:00
include ARM: Separate the early console (romstage) from the bootblock console. 2013-06-13 21:15:40 -07:00
lib Make elog_shrink not depend on having seperate memory/flash descriptors. 2013-06-14 16:15:30 -07:00
mainboard peppy: Add an inverted input GPIO type 2013-06-17 15:26:11 -07:00
northbridge haswell: Update pei_data to match ref code 2013-06-04 12:53:42 -07:00
southbridge lynxpoint: update EHCI pci ids 2013-06-13 22:16:10 -07:00
superio Drop prototype guarding for romcc 2013-05-10 11:55:20 -07:00
vendorcode vboot: use out_flags to indicate recovery mode 2013-06-04 12:53:47 -07:00
Kconfig BACKPORT: x86: add thread support 2013-05-15 11:19:50 -07:00