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exynos5420: add I2C8-10 to clock_get_periph_rate()

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This adds entries for I2C8-10 to giant switch statement in
clock_get_periph_rate(). It also eliminates the I2C peripheral's
usage of clk_bit_info since it's confusing and error-prone.

BUG=chrome-os-partner:19420
BRANCH=none
TEST=TODO...

Change-Id: I4b006c034575e6bd1f4722503668b9a142020eb5
Reviewed-on: https://gerrit.chromium.org/gerrit/58782
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks 2013-06-15 19:22:06 -07:00 • committed by ChromeBot
commit 5b9598b74c
2 changed files with 9 additions and 10 deletions
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16
src/cpu/samsung/exynos5420/clock.c
View file

@ -47,14 +47,7 @@ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
{4, 12, 16},
{-1, -1, -1},
{-1, -1, -1},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
[PERIPH_ID_DPHPD]
{24, 0, -1},
{24, 0, -1},
{24, 0, -1},
@ -200,9 +193,12 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
case PERIPH_ID_I2C8:
case PERIPH_ID_I2C9:
case PERIPH_ID_I2C10:
sclk = get_pll_clk(MPLL);
sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) & 0x7) + 1;
div = ((readl(&clk->div_top0) >> bit_info->prediv_bit) & 0x7) + 1;
sub_div = ((readl(&clk->div_top1) >> 24) & 0x7) + 1;
div = (readl(&clk->div_top0) & 0x7) + 1;
return (sclk / sub_div) / div;
default:
printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral);

3
src/cpu/samsung/exynos5420/periph.h
View file

@ -53,6 +53,9 @@ enum periph_id {
PERIPH_ID_I2C5,
PERIPH_ID_I2C6,
PERIPH_ID_I2C7,
PERIPH_ID_I2C8,
PERIPH_ID_I2C9,
PERIPH_ID_I2C10,
PERIPH_ID_DPHPD, /* eDP hot plug detect */
PERIPH_ID_PWM0,
PERIPH_ID_PWM1,