coreboot/src/soc/amd
Maximilian Brune 5aebeb4056 soc/amd/glinda/chipset.cb: Enable gpp_bridge_[a/b/c] by default
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.

In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.

Change-Id: Id28a29481f9a1bc570e47a9cb75613d3621b0d44
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86270
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-02-15 21:28:55 +00:00
..
cezanne soc/amd/common/block/graphics: Use vbt_get() 2025-02-14 16:35:34 +00:00
common device/pci_rom: Move VBIOS checksum fix 2025-02-14 16:41:41 +00:00
genoa_poc drivers/amd/opensil/acpi.c: Factor common ACPI calls to openSIL driver 2025-01-28 20:18:07 +00:00
glinda soc/amd/glinda/chipset.cb: Enable gpp_bridge_[a/b/c] by default 2025-02-15 21:28:55 +00:00
mendocino soc/amd/common/block/graphics: Use vbt_get() 2025-02-14 16:35:34 +00:00
phoenix soc/amd/common/block/graphics: Use vbt_get() 2025-02-14 16:35:34 +00:00
picasso soc/amd/common/block/graphics: Use vbt_get() 2025-02-14 16:35:34 +00:00
stoneyridge tree: Remove unused <assert.h> 2024-11-19 00:40:04 +00:00