When allowing use of SSE instructions, stack must be
aligned to 16 bytes. Adjust x86 entry to C accordingly,
by pushing values to maintain the alignment.
For some builds, new toolchain and GCC-6.3 could emit
SSE instruction 'andps (%esp),%xmm0' with incorrectly
aligned esp, raising exception and thus preventing boot.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8cf0cd97d9191e23f1f9ce0b8ae647f523a076cd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id:
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| .. | ||
| acpi | ||
| arch | ||
| commonlib | ||
| console | ||
| cpu | ||
| device | ||
| drivers | ||
| ec | ||
| include | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| soc | ||
| southbridge | ||
| superio | ||
| vboot | ||
| vendorcode | ||
| Kconfig | ||