coreboot/src/soc/nvidia
Yen Lin 8c70625ad4 t132: tegra_lp0_resume: configure debug uart to 115200n8
Need to configure debug uart port to have proper baudrate/width/parity.
Hard-code it to 115200n8.

BUG=chrome-os-partner:32015
BRANCH=None
TEST=successfully suspend/resume on Rush/Ryu

Change-Id: I6a96c80654ce52f5b877fd46995ca8c1aceb7017
Signed-off-by: Yen Lin <yelin@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/226407
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2014-11-04 01:34:58 +00:00
..
tegra gpio: Extend common GPIO header, simplify function names 2014-10-22 04:06:14 +00:00
tegra124 vboot: move vboot files to designated directory 2014-10-22 19:44:12 +00:00
tegra132 t132: tegra_lp0_resume: configure debug uart to 115200n8 2014-11-04 01:34:58 +00:00
Kconfig coreboot tegra132: Add support for tegra132 soc 2014-06-10 00:13:43 +00:00
Makefile.inc coreboot tegra132: Add support for tegra132 soc 2014-06-10 00:13:43 +00:00