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coreboot/src/include/cpu/intel
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Jeremy Compostella 1eff77bc59 arch/x86: Reduce max phys address size for Intel TME capable SoCs 
On Intel SoCs, if TME is supported, TME key ID bits are reserved and
should be subtracted from the maximum physical addresses available.

BUG=288978352
TEST=Verified that DMAR ACPI table `Host Address Width` field on rex
     went from 45 to 41.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-12 08:12:02 +00:00
..
cpu_ids.h treewide: Drop the suffixes from ADL and RPL CPUID macros and strings 2023-07-12 13:53:40 +00:00
em64t100_save_state.h src/include: Drop unneeded empty lines 2020-09-14 07:09:41 +00:00
em64t101_save_state.h src/include: Drop unneeded empty lines 2020-09-14 07:09:41 +00:00
fsb.h treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
l2_cache.h treewide: Remove 'extern' from functions declaration 2023-05-26 13:45:24 +00:00
microcode.h cpu/intel/microcode: Have API to re-load microcode patch 2022-06-22 12:35:53 +00:00
msr.h arch/x86: Reduce max phys address size for Intel TME capable SoCs 2023-09-12 08:12:02 +00:00
post_codes.h src/*/post_code.h: Change post code prefix to POSTCODE 2023-08-05 16:04:46 +00:00
smm_reloc.h mb/emulation/qemu-q35: Split smm_close() and smm_lock() 2022-11-17 07:42:55 +00:00
speedstep.h cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm 2022-12-05 14:22:12 +00:00
turbo.h treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00