Jeremy Compostella 1eff77bc59 arch/x86: Reduce max phys address size for Intel TME capable SoCs ... On Intel SoCs, if TME is supported, TME key ID bits are reserved and should be subtracted from the maximum physical addresses available. BUG=288978352 TEST=Verified that DMAR ACPI table `Host Address Width` field on rex went from 45 to 41. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>		2023-09-12 08:12:02 +00:00
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amd	include/cpu/amd/msr: introduce and use PSTATE_MSR_COUNT	2023-07-18 21:51:33 +00:00
intel	arch/x86: Reduce max phys address size for Intel TME capable SoCs	2023-09-12 08:12:02 +00:00
power	src/cpu/power9: move part of scom.h to scom.c	2023-04-18 13:05:56 +00:00
x86	arch/x86: Ensure LAPIC mode for exception handler	2023-07-05 15:59:31 +00:00
cpu.h	cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_path	2023-04-06 15:13:28 +00:00