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Jeffy Chen 574bdfa22d google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration
Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto.

BUG=chrome-os-partner:56759
BRANCH=none
TEST=Build

Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/381801
Commit-Queue: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
Trybot-Ready: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-09-07 05:36:01 +00:00
configs Fievel: Add veyron_fievel board for coreboot 2016-05-18 00:10:05 +00:00
documentation documentation: Add documentation for timestamp library 2014-11-14 23:57:04 +00:00
payloads Fievel: Add veyron_fievel board for coreboot 2016-05-18 00:10:05 +00:00
src google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration 2016-09-07 05:36:01 +00:00
util Force gnu bfd linker for coreboot. 2015-03-04 21:38:51 +00:00
.gitignore rmodules: add support for rmodtool 2014-03-31 22:25:57 +00:00
COMMIT-QUEUE.ini COMMIT-QUEUE.ini: Add documentation. 2013-11-01 14:08:42 +00:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile Makefile: Fix dependency tracking for ramstage objects 2014-12-06 01:10:41 +00:00
Makefile.inc Makefile: Fix dependency tracking for ramstage objects 2014-12-06 01:10:41 +00:00
PRESUBMIT.cfg chromeos: Add PRESUBMIT.cfg 2013-05-01 14:31:10 -07:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00
toolchain.inc ARM: Remove -mno-unaligned-access 2015-01-21 01:17:51 +00:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.