David Hendricks 56144ddf1f exynos5420: init APLL at 1800MHz ... This initializes the APLL at 1800MHz. BUG=none BRANCH=none TEST=built and booted on Pit Change-Id: I366bf4e75510847ab93d9c9f214a49c731cca08a Reviewed-on: https://gerrit.chromium.org/gerrit/64745 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org>		2013-08-07 15:24:59 -07:00
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arch	armv7: add wrappers to read/write L2ACTLR	2013-08-07 12:43:20 -07:00
console	Don't try to use CBMEM console in bootblock	2013-06-20 15:51:33 -07:00
cpu	exynos5420: init APLL at 1800MHz	2013-08-07 15:24:59 -07:00
device	Log device path during resource allocation	2013-07-09 13:27:45 -07:00
drivers	Patch to refactor code containing aux calls	2013-08-02 17:32:37 -07:00
ec	chromeec: Add event methods for EC requested throttle	2013-08-01 00:30:25 -07:00
include	Timestamp implementation for ARMv7	2013-08-02 12:16:42 -07:00
lib	Pit: graphics	2013-08-05 20:53:23 -07:00
mainboard	snow: Set up the i2s0 pins during boot.	2013-08-07 13:35:45 -07:00
northbridge	haswell: Add pei_data field for USB routing	2013-07-31 13:15:53 -07:00
southbridge	lynxpoint: XHCI: Advertise D3 as lowest wake state	2013-07-31 13:15:56 -07:00
superio	Drop prototype guarding for romcc	2013-05-10 11:55:20 -07:00
vendorcode	Rename cpu/x86/car.h to arch/early_variables.h	2013-07-30 13:40:23 -07:00
Kconfig	Add a HAVE_ARCH_MEMMOVE option to allow overriding memmove.	2013-07-08 11:30:26 -07:00