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armv7: add wrappers to read/write L2ACTLR

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This adds inline wrappers to read the L2 cache auxiliary control
register (L2ACTLR).

Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
BRANCH=none
TEST=it builds (tested more thoroughly w/ follow-up patches)

Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f
Reviewed-on: https://gerrit.chromium.org/gerrit/64861
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks 2013-08-06 17:32:41 -07:00 • committed by ChromeBot
commit b842e93f82
2 changed files with 30 additions and 0 deletions
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15
payloads/libpayload/include/armv7/arch/cache.h
View file

@ -240,6 +240,21 @@ static inline void write_l2ctlr(uint32_t val)
isb();
}
/* read L2 Auxiliary Control Register (L2ACTLR) */
static inline uint32_t read_l2actlr(void)
{
uint32_t val = 0;
asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
return val;
}
/* write L2 Auxiliary Control Register (L2ACTLR) */
static inline void write_l2actlr(uint32_t val)
{
asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
isb();
}
/* read system control register (SCTLR) */
static inline uint32_t read_sctlr(void)
{

15
src/arch/armv7/include/arch/cache.h
View file

@ -246,6 +246,21 @@ static inline void write_l2ctlr(uint32_t val)
isb();
}
/* read L2 Auxiliary Control Register (L2ACTLR) */
static inline uint32_t read_l2actlr(void)
{
uint32_t val = 0;
asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
return val;
}
/* write L2 Auxiliary Control Register (L2ACTLR) */
static inline void write_l2actlr(uint32_t val)
{
asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
isb();
}
/* read system control register (SCTLR) */
static inline uint32_t read_sctlr(void)
{