coreboot/src/vendorcode
Patrick Georgi 00d48464b9 build system: remove intermediate link step in vboot
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I5405c0ee6bee203281e723feaecaee57fad8f6cb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29 22:41:26 +02:00
..
amd AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2 2015-03-07 21:22:20 +01:00
google build system: remove intermediate link step in vboot 2015-03-29 22:41:26 +02:00
intel intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP 2015-01-31 23:09:26 +01:00
Kconfig AMD Steppe Eagle: Add binary PI vendorcode files 2014-08-30 19:13:45 +02:00
Makefile.inc Add Intel FSP northbridge support Sandybridge and Ivybridge 2013-12-04 18:45:13 +01:00