coreboot/src
Patrick Georgi 00d48464b9 build system: remove intermediate link step in vboot
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I5405c0ee6bee203281e723feaecaee57fad8f6cb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29 22:41:26 +02:00
..
arch mips: add verstage configuration 2015-03-29 22:38:53 +02:00
console arm64: Add support for secure monitor 2015-03-28 07:05:09 +01:00
cpu mips: add verstage configuration 2015-03-29 22:38:53 +02:00
device PCIe: Revise L1 Sub-State support 2015-03-23 13:11:18 +01:00
drivers drivers/pc80/mc146818rtc_early: Honor Kconfig reboot count clear setting 2015-03-29 00:42:34 +01:00
ec chromeec: Add ACPI device for PD MCU and handle related EC host event 2015-03-27 06:30:44 +01:00
include arch/x86/boot/smbios: Rename fill_dimm_manufacturer and make public 2015-03-29 16:34:07 +02:00
lib arm64: Add support for secure monitor 2015-03-28 07:05:09 +01:00
mainboard mainboard/asus/kfsn4-dre: Enable BIOS recovery jumper 2015-03-29 08:44:34 +02:00
northbridge build system: normalize linker script file names 2015-03-28 19:14:47 +01:00
soc pistachio: don't open code ramstage loading 2015-03-28 17:43:47 +01:00
southbridge build system: normalize linker script file names 2015-03-28 19:14:47 +01:00
superio superio: ite8772f: Exit extemp busy state 2015-03-21 08:44:28 +01:00
vendorcode build system: remove intermediate link step in vboot 2015-03-29 22:41:26 +02:00
Kconfig Enable publishing of board ID where supported 2015-03-23 17:20:24 +01:00