coreboot/src
Duncan Laurie 55228ba4b4 broadwell: Changes from 2.2.0 ref code
- The SATA CAP register setup was moved outside the refcode blob we run
so it needs to be set up by coreboot again...
- Slight tweak to fast ramp voltage for broadwell CPU

BUG=chrome-os-partner:25491
BRANCH=None
TEST=Build and boot on samus

Original-Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173
Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-CReviewed-on: https://chromium-review.googlesource.com/214024
Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5d166a0c4d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id58d3bee5e713139edf6e8fda8cdf4c48ba95bd1
Reviewed-on: http://review.coreboot.org/8964
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27 06:20:36 +01:00
..
arch arm64: Seed the stack at stage_entry 2015-03-26 00:27:54 +01:00
console console: Convert cbmem log line endings to UNIX standard 2015-03-25 17:25:14 +01:00
cpu cpu/amd/model_10xxx: Increase preram buffer size to 32k 2015-03-25 17:26:48 +01:00
device PCIe: Revise L1 Sub-State support 2015-03-23 13:11:18 +01:00
drivers vboot2: read secdata and nvdata 2015-03-23 19:51:47 +01:00
ec chromeec: use stopwatch API 2015-03-21 17:00:26 +01:00
include timer: remove rela_time type 2015-03-26 08:53:53 +01:00
lib cbfs: support concurrent media channels properly 2015-03-26 08:53:39 +01:00
mainboard samus: Updates for EVT board 2015-03-27 06:19:45 +01:00
northbridge cpu/amd/model_10xxx: Add support for early cbmem 2015-03-19 08:28:43 +01:00
soc broadwell: Changes from 2.2.0 ref code 2015-03-27 06:20:36 +01:00
southbridge CBMEM: Add LATE_CBMEM_INIT guards 2015-03-19 06:17:07 +01:00
superio superio: ite8772f: Exit extemp busy state 2015-03-21 08:44:28 +01:00
vendorcode Chrome OS vendorcode: Fix vboot_reference compilation 2015-03-26 03:07:18 +01:00
Kconfig Enable publishing of board ID where supported 2015-03-23 17:20:24 +01:00