coreboot/src/soc
Subrata Banik 5489341e63 soc/intel/icelake: Add chipset event logging
This patch ports CB:30718 and CB:31908 changes from CNL to ICL.

Add logging of chipset events on boot into the flash event log.
This was tested on a google/dragonegg board to ensure that events
like "System Reset" are added to the log as expected.

Also fix GEN_PMCON bit checks as below:
ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.

Change-Id: I25ec32e81f8801f8d5e69c6095ffed73d75dded6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-05-02 06:02:52 +00:00
..
amd soc/{amd,intel}/chip: Use local include for chip.h 2019-04-26 16:49:13 +00:00
cavium soc/cavium/common/bootblock: Remove unused variables 2019-04-25 15:55:27 +00:00
imgtec arch/mips: Fix <arch/mmio.h> prototypes 2019-03-22 12:18:41 +00:00
intel soc/intel/icelake: Add chipset event logging 2019-05-02 06:02:52 +00:00
mediatek vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
nvidia vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
qualcomm vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
rockchip rockchip: rk3399: increase memory for fit payload. 2019-04-30 22:38:10 +00:00
samsung src: include <assert.h> when appropriate 2019-04-23 10:01:36 +00:00
sifive src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller 2019-03-18 09:12:46 +00:00
ucb riscv: Add initial support for 32bit boards 2019-02-13 04:49:14 +00:00