coreboot/src
Subrata Banik 5489341e63 soc/intel/icelake: Add chipset event logging
This patch ports CB:30718 and CB:31908 changes from CNL to ICL.

Add logging of chipset events on boot into the flash event log.
This was tested on a google/dragonegg board to ensure that events
like "System Reset" are added to the log as expected.

Also fix GEN_PMCON bit checks as below:
ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.

Change-Id: I25ec32e81f8801f8d5e69c6095ffed73d75dded6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-05-02 06:02:52 +00:00
..
acpi arch/x86: Add common AMD ACPI hardware definitions 2017-11-10 19:15:38 +00:00
arch arch/x86/acpi: Update VT-d DMA remapping structure flags setting 2019-05-01 18:33:55 +00:00
commonlib src: include <assert.h> when appropriate 2019-04-23 10:01:36 +00:00
console coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
cpu cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE 2019-04-25 15:56:28 +00:00
device x86emu: add console.h header to fix compilation 2019-05-02 05:00:33 +00:00
drivers drivers/spi/sst: Remove unused variables 2019-04-25 15:55:10 +00:00
ec ec/google/wilco: Support board_id with EC provided ID 2019-04-18 23:43:06 +00:00
include lib/fmap: Add area read/write functions 2019-04-23 10:22:54 +00:00
lib vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
mainboard mb/google/sarien: Disable S5 wake on LAN by default 2019-05-01 20:07:48 +00:00
northbridge vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
security vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
soc soc/intel/icelake: Add chipset event logging 2019-05-02 06:02:52 +00:00
southbridge sb/intel/bd82x6x: Use system_reset() 2019-04-29 16:01:36 +00:00
superio superio/fintek/f71808a: Add more optional ramstage registers 2019-05-01 00:09:57 +00:00
vendorcode coreboot: Run mainboard specific code before Cr50 reset 2019-04-23 10:21:24 +00:00
Kconfig src/Kconfig: increase heap size if using flattened image tree 2019-04-24 20:42:52 +00:00