359ae67668
Use POSTPONE_SPI_ACCESS to handle elog data later boot phase to avoid flash access delay by other boot controllers. Intel has pre-CPU boot controllers (e.g. CSE) which load non-CPU firmwares. Boot-critical firmwares are loaded before CPU reset and non-boot-critical firmwares are loaded during CPU boot. If another controller accesses SPI to load firmwares, reading SPI by CPU is ok, but writing to SPI for saving elog data can take ~32ms sometimes. Saving elog data usually takes less than 1ms. There are three elog handling sequences that need to move together under the Kconfig: - Soc folder - Elog driver folder - ChromeOS folder Before this change, sometimes it delays like below: BS: callback (0x7386d428) @ src/soc/intel/pantherlake/elog.c:216 (32 ms) After this change, the delay is less than 1 ms: BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms) TEST 1. Enable DEBUG_BOOT_STATE 2. Check time BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)) Change-Id: I3f5e7acf5204e213179664d0d77151d415d00896 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> |
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| eltan | ||
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| Makefile.mk | ||
| README.md | ||
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