USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI USB2 port reset event issued by the xHCI driver shall trigger a message upstream to CPU to wake it from the low power state which allows a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Built and booted to kernel on Voxel board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| alderlake | ||
| apollolake | ||
| baytrail | ||
| braswell | ||
| broadwell | ||
| cannonlake | ||
| common | ||
| denverton_ns | ||
| elkhartlake | ||
| icelake | ||
| jasperlake | ||
| quark | ||
| skylake | ||
| tigerlake | ||
| xeon_sp | ||
| Kconfig | ||