John Zhao 4ead6b3367 soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports ... USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI USB2 port reset event issued by the xHCI driver shall trigger a message upstream to CPU to wake it from the low power state which allows a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Built and booted to kernel on Voxel board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-01-08 08:22:47 +00:00
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amd	soc/amd/picasso: Generate GNB IO-APIC PCI routing table	2021-01-08 08:12:53 +00:00
cavium	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
example	arch/x86: Move prologue to .init section	2021-01-07 11:02:03 +00:00
intel	soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports	2021-01-08 08:22:47 +00:00
mediatek	soc/mediatek: rtc: Use bool as return type	2021-01-07 02:02:51 +00:00
nvidia	Makefile: Add $(xcompile) to specify where to write xcompile	2020-12-23 03:40:35 +00:00
qualcomm	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
rockchip	drivers: Replace set_vbe_mode_info_valid	2020-12-17 06:21:56 +00:00
samsung	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
sifive	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
ti	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00