0a867b3971
Based on AMD doc #48882 PUB Rev 3.10 [1]. Now, the IVHD type 11h and 40h have a second 64bit EFR value that should be filled with IOMMU MMIO offset 0x1A0 register value if EFR is supported. [1] https://docs.amd.com/v/u/en-US/48882_IOMMU Change-Id: I0da79bed8994671c651328cd7a29d9480a122528 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> |
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| .. | ||
| acpi.h | ||
| acpi_apei.h | ||
| acpi_crat.h | ||
| acpi_device.h | ||
| acpi_gnvs.h | ||
| acpi_iort.h | ||
| acpi_ivrs.h | ||
| acpi_osc.h | ||
| acpi_pld.h | ||
| acpi_pm.h | ||
| acpi_sata.h | ||
| acpi_soundwire.h | ||
| acpigen.h | ||
| acpigen_dptf.h | ||
| acpigen_dsm.h | ||
| acpigen_pci.h | ||
| acpigen_ps2_keybd.h | ||
| acpigen_usb.h | ||