Arthur Heymans 481599f2c8 soc/intel/fast_spi: Use smarter mtrr code in ramstage ... mtrr_use_temp_range is a lot smarter than the plain set_var_mtrr. It will compute a new optimal solution with the temp ranges included while also taking care of the cleanup before loading the payload/s3 resume. Change-Id: I283ba07fc12c410be39dfdc828657598237247c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63550 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2022-06-01 09:48:54 +00:00
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amd	soc/amd/sabrina/acpi/soc.asl: re-enable WAL1 call in PNOT method	2022-05-28 04:43:53 +00:00
cavium	i2c: Add configurable I2C transfer timeout	2022-03-15 22:06:27 +00:00
example
intel	soc/intel/fast_spi: Use smarter mtrr code in ramstage	2022-06-01 09:48:54 +00:00
mediatek	soc/mediatek/mt8192: Enable thermal hardware reset	2022-05-28 04:27:19 +00:00
nvidia	soc/*: Use __fallthrough statement	2022-05-11 06:04:25 +00:00
qualcomm	qclib common code clean up changes	2022-06-01 01:32:00 +00:00
rockchip	soc/*: Use __fallthrough statement	2022-05-11 06:04:25 +00:00
samsung	i2c: Add configurable I2C transfer timeout	2022-03-15 22:06:27 +00:00
sifive
ti	treewide: Remove "ERROR: "/"WARN: " prefixes from log messages	2022-02-07 23:29:09 +00:00
ucb