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There's two copies of the `get_cxl_mode()` function to map the OCP VPD value to the values expected by platform code. As this is unnecessary, have a single copy of this function in the OCP VPD driver code. As the `get_cxl_mode()` function is Xeon-SP only, keep it in a separate file. This change simplifies things for boards using OCP VPD for CXL and has no impact for boards *not* using OCP VPD: - Boards not using OCP VPD can still define get_cxl_mode() in mainboard code as needed, just like they were able to do before. - Boards using OCP VPD but without CXL (`SOC_INTEL_HAS_CXL` is not enabled), this code won't get compiled in at all (see `Makefile.mk`). - Boards using OCP VPD and CXL will automatically make use of this `get_cxl_mode()` definition, which should be the same for all boards. It is possible that this may need to be expanded/adapted in the future, which is easy to handle in a follow-up commit when the need arises. TEST=Build and boot on intel/archercity CRB Change-Id: I935c4eb5b2392e2d0dc01b9f66d46c79b8141ea7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82224 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> |
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