coreboot/src
Mike Loptien 42ad200657 Lippert Fam14 DSDT: Add secondary bus range to PCI0
Adding the 'WordBusNumber' macro to the PCI0
CRES ResourceTemplate in the Persimmon DSDT.
This sets up the bus number for the PCI0 device
and the secondary bus number in the CRS method.
This change came in response to a 'dmesg' error
which states:
'[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'

By adding the 'WordBusNumber' macro, ACPI can set
up a valid range for the PCIe downstream busses,
thereby relieving the Linux kernel from "guessing"
the valid range based off _BBN or assuming [0-0xFF].
The Linux kernel code that checks this bus range is
in `drivers/acpi/pci_root.c`.  PCI busses can have
up to 256 secondary busses connected to them via
a PCI-PCI bridge.  However, these busses do not
have to be sequentially numbered, so leaving out a
section of the range (eg. allowing [0-0x7F]) will
unnecessarily restrict the downstream busses.

This is the same change as made to Persimmon with
change-id I44f22:
http://review.coreboot.org/#/c/2592/

Change-Id: Ie36b60973c6a5f9076bb55c8f451532711a2f8a8
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2737
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-17 19:55:03 +01:00
..
arch Google Link: Add remaining code to support native graphics 2013-03-15 20:21:51 +01:00
console Eliminate do_div(). 2013-03-08 23:14:26 +01:00
cpu Google Link: Add remaining code to support native graphics 2013-03-15 20:21:51 +01:00
device Google Link: Add remaining code to support native graphics 2013-03-15 20:21:51 +01:00
drivers GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
ec Support ITE IT8518 embedded controller running Quanta's firmware 2013-03-14 04:54:21 +01:00
include stddef.h: Add standard defines for KiB, MiB, GiB, and TiB 2013-03-16 16:15:01 +01:00
lib Eliminate do_div(). 2013-03-08 23:14:26 +01:00
mainboard Lippert Fam14 DSDT: Add secondary bus range to PCI0 2013-03-17 19:55:03 +01:00
northbridge haswell: don't add a 0-sized memory range resource 2013-03-16 04:58:18 +01:00
southbridge lynxpoint: Add support for disabling ULT devices 2013-03-17 00:36:24 +01:00
superio Super I/O W83627DHG: Enable UART B by redirecting pins 2013-03-15 17:51:48 +01:00
vendorcode google/snow: rename a file so that it is clear what board it is for 2013-03-16 04:07:35 +01:00
Kconfig bump SeaBIOS to 1.7.2.1 2013-03-04 11:00:17 +01:00