If a port is connected before and after an xhci controller reset, the PORTSC CSC bit may not be asserted. Add an additional check in xhci_rh_port_status_changed for the PRC bit so we can correctly handle ports in such a state. BUG=chrome-os-partner:24090 TEST=Manual on Rambi: - Boot Chromium OS from USB 3.0 drive - Issue 'reboot' on command line - Boot from USB 3.0 drive again successfully Also -- - Boot Chromium OS from USB 3.0 drive - Issue 'reboot' on command line - Boot Chromium OS from eMMC - Issue 'reboot' on command line - Boot from USB 3.0 drive again successfully Also, verify that USB ports continue to function correctly, and USB 3.0 device is always detected in Chromium OS as a superspeed device. BRANCH=Rambi Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I2d623aae647ab13711badd7211ab467afdc69548 Reviewed-on: https://chromium-review.googlesource.com/189394 Reviewed-by: Julius Werner <jwerner@chromium.org> |
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| .. | ||
| bayou | ||
| coreinfo | ||
| external | ||
| libpayload | ||
| nvramcui | ||
| tianocoreboot | ||
| ubootcli | ||