coreboot/src/soc
Martin Roth 3a54318856 Add EM100 'hyper term' spi console support in ramstage & smm
The EM100Pro allows the debug console to be sent over the SPI bus.
This is not yet working in romstage due to the use of static variables
in the SPI driver code.  It is also not working on chipsets that have
SPI write buffers of less than 10 characters due to the 9 byte
command/header length specified by the EM100 protocol.

While this currently works only with the EM100, it seems like it would
be useful on any logic analyzer with SPI debug - just filter on command
bytes of 0x11.

Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-05 17:43:11 +00:00
..
broadcom/cygnus broadcom/cygnus: remove verstage.c 2015-10-02 12:16:21 +00:00
imgtec/pistachio linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
intel Add EM100 'hyper term' spi console support in ramstage & smm 2015-10-05 17:43:11 +00:00
marvell/bg4cd linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
nvidia tegra124: use the common verstage flow 2015-10-02 12:16:35 +00:00
qualcomm/ipq806x linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
rockchip/rk3288 linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
samsung linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
ucb/riscv Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00