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tegra124: use the common verstage flow

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Though the tegra124 SoC makes their faster cpus come up
in verstage it can still use the common flow. Therefore,
use the common verstage API for performing thenecessary
steps to initialize the caches on the faster cores.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built nyan.

Change-Id: I93023ec92a9de111db688742b057b5c64143f0b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11776
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin 2015-10-01 16:24:28 -05:00
commit 5a4f289c42
1 changed files with 3 additions and 12 deletions
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15
src/soc/nvidia/tegra124/verstage.c
View file

@ -27,6 +27,7 @@
#include <soc/early_configs.h>
#include <stdlib.h>
#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void enable_cache(void)
{
@ -40,27 +41,17 @@ static void enable_cache(void)
dcache_mmu_enable();
}
/* Do the minimum to run vboot at full speed */
static void soc_init(void)
void verstage_mainboard_init(void)
{
/* Do the minimum to run vboot at full speed */
configure_l2_cache();
console_init();
exception_init();
enable_cache();
}
static void verstage(void)
{
soc_init();
early_mainboard_init();
run_romstage();
}
void main(void)
{
asm volatile ("bl arm_init_caches"
: : : "r0", "r1", "r2", "r3", "r4", "r5", "ip");
verstage();
hlt();
}