Kane Chen 374f27bc02 baytrail: there is a chance that USBPHY_COMPBG is set to 0 ... Due to some projects don't have the correct settings in devicetree.cb so put this change in case those projects without are setting in devicetree.cb BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly even there is no setting in devicetree Original-Change-Id: Iaf8155497c41f10c81d1faa7bb0e3452a7cedcc6 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209051 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 713f809952) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I86f9b77e703d2b844fa636678499c47ffaffeede Reviewed-on: http://review.coreboot.org/8218 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2015-01-16 20:50:40 +01:00
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intel	baytrail: there is a chance that USBPHY_COMPBG is set to 0	2015-01-16 20:50:40 +01:00
nvidia	Revert "vboot2: add verstage"	2015-01-14 19:28:19 +01:00
qualcomm	storm: Reserve memory from 0x4000_0000-0x414f_ffff	2015-01-09 06:21:08 +01:00
samsung	doxygen fixes: change @var to @param var	2015-01-06 06:33:25 +01:00
ucb	soc/riscv: Fix typo in src/soc/ucb/Makefile.inc.	2015-01-01 18:07:14 +01:00
Kconfig	Add UCB RISCV support for architecture, soc, and emulation mainboard..	2014-12-01 19:06:43 +01:00
Makefile.inc	Add UCB RISCV support for architecture, soc, and emulation mainboard..	2014-12-01 19:06:43 +01:00