Duncan Laurie c0e22ba043 broadwell: Misc updates from 2.1.0 ref code ... - ADSP IRQ should be exclusive - HDA should write reg 0x43 even if disabled - A few clock gating tweaks based on ref code changes - Move SATA clock gating to sata.c where SIR changes are done - Add support for enabling Deep SX in AC/DC modes - CLKREQ VR Idle for enabled PCIE ports BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/211611 Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2014-08-08 22:02:33 +00:00
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baytrail	baytrail: there is a chance that USBPHY_COMPBG is set to 0	2014-07-20 07:47:12 +00:00
broadwell	broadwell: Misc updates from 2.1.0 ref code	2014-08-08 22:02:33 +00:00
common	baytrail: Move HDA verb table to Intel SOC common directory	2014-04-23 02:47:34 +00:00
Kconfig	broadwell: Hook into the build system	2014-05-15 05:15:08 +00:00
Makefile.inc	broadwell: Hook into the build system	2014-05-15 05:15:08 +00:00