Hung-Te Lin 28a634857b exynos5420: Setup clocks for MMC bus controller. ... To configure source clocks on Exynos 5420 for MMC drivers. Some registers are different from the 5250. FSYS now has two parts and MMC uses FSYS2. The MMC block uses MPLL as the clock source. The "high-speed" MMC interface runs as 52MHz, so divider is set accordingly. Also, the MMC driver has changed from MSHCI (Mobile Storage Host Controller Interface) to DWMCI (DesignWare MMC Controller Interface). BUG=chrome-os-partner:19420 BRANCH=none TEST=emerge-peach_pit chromeos-coreboot-peach_pit Change-Id: I9ba9cf43e2f2dcd9da747888c0c7676bd545177b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60858 Reviewed-by: David Hendricks <dhendrix@chromium.org>		2013-07-10 11:16:00 -07:00
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amd	copy_and_run: drop boot_complete parameter	2013-05-10 11:55:19 -07:00
armltd	qemu-armv7 CPU: Move Kconfig code into CPU directory	2013-06-20 15:51:33 -07:00
intel	haswell: Update ULT microcode to rev 14h	2013-07-09 12:25:08 -07:00
samsung	exynos5420: Setup clocks for MMC bus controller.	2013-07-10 11:16:00 -07:00
via	copy_and_run: drop boot_complete parameter	2013-05-10 11:55:19 -07:00
x86	BACKPORT: x86: add cache-as-ram migration option	2013-05-16 15:06:24 -07:00
Kconfig	Simplify early / bootblock console code	2013-06-20 13:54:33 -07:00
Makefile.inc	cpu: Add CPU microcode file to cbfs with 16-byte alignment	2013-06-12 06:55:42 -07:00