coreboot/src
Gabe Black 28603b21d4 exynos5420: Revamp the high speed I2C driver.
The previous driver was a bit awkward and not entirely correct. This change
primarily replaces the read/write functions with simpler and more robust
(hopefully) version.

BUG=chrome-os-partner:19420
TEST=Built and booted on pit into the RAM stage without any errors reading or
writing registers on the PMIC. There isn't really any direct feedback from the
PMIC, so I'm assuming since it didn't complain it worked. I looked at some of
the transaction on an oscilloscope and they looked correct.
BRANCH=None

Change-Id: I01b1f9ea43eafb4aae1dbebddc051cd5ec5aea74
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59201
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
2013-06-20 02:14:18 -07:00
..
arch arm: Fix memory barrier usage in IO operation 2013-06-18 22:19:43 -07:00
console ARM: Separate the early console (romstage) from the bootblock console. 2013-06-13 21:15:40 -07:00
cpu exynos5420: Revamp the high speed I2C driver. 2013-06-20 02:14:18 -07:00
device Clean up POST codes for Boot State machine 2013-06-10 18:08:24 -07:00
drivers max77802: add header for max77802 PMIC 2013-06-18 17:08:17 -07:00
ec ec: Reserve correct ioport regions for Chrome OS EC to use 2013-06-12 14:02:10 -07:00
include ARM: Separate the early console (romstage) from the bootblock console. 2013-06-13 21:15:40 -07:00
lib Make elog_shrink not depend on having seperate memory/flash descriptors. 2013-06-14 16:15:30 -07:00
mainboard pit: set up the PMIC correctly 2013-06-18 20:31:34 -07:00
northbridge haswell: Update pei_data to match ref code 2013-06-04 12:53:42 -07:00
southbridge lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects 2013-06-19 15:22:49 -07:00
superio Drop prototype guarding for romcc 2013-05-10 11:55:20 -07:00
vendorcode vboot: use out_flags to indicate recovery mode 2013-06-04 12:53:47 -07:00
Kconfig BACKPORT: x86: add thread support 2013-05-15 11:19:50 -07:00