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coreboot/src/cpu
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Gabe Black 4f3873d2ce arm: Get rid of the INTERMEDIATE variable used on exynos. 
The INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for
Exynos SOCs, but we can do that directly without having a special hook.

Change-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/170921
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8db03c387a)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6714
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-21 18:44:56 +02:00
..
allwinner src: Make use of 'CEIL_DIV(a, b)' macro across tree 2014-07-11 08:39:07 +02:00
amd cpu/amd/geode_lx: Trivial - remove useless comment 2014-08-09 18:32:11 +02:00
armltd Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
dmp Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
intel cpu/intel/fsp_model_406dx: code cleanup 2014-08-18 02:22:09 +02:00
qemu-x86 Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
samsung arm: Get rid of the INTERMEDIATE variable used on exynos. 2014-08-21 18:44:56 +02:00
ti Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
via Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
x86 x86/smm/smihandler.c: break case in switch 2014-08-11 17:03:45 +02:00
Kconfig Move ARCH_* from board/Kconfig to cpu or soc Kconfig. 2014-05-03 00:25:20 +02:00
Makefile.inc armv7/Makefile.inc, cpu/Makefile.inc: align output of printf 2014-08-12 09:02:43 +02:00