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arm: Get rid of the INTERMEDIATE variable used on exynos.

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The INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for
Exynos SOCs, but we can do that directly without having a special hook.

BUG=None
TEST=Built for pit and snow and verified that the BL1 was still copied into
the image as expected.
BRANCH=None

Change-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/170921
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-09-26 23:21:57 -07:00 • committed by chrome-internal-fetch
commit 8db03c387a
3 changed files with 11 additions and 11 deletions
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2
src/arch/armv7/Makefile.inc
View file

@ -61,7 +61,7 @@ $(obj)/coreboot.pre1: $(CBFSTOOL)
mv $(obj)/coreboot.rom $@
endif
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE)
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES))
@printf " CBFS $(subst $(obj)/,,$(@))\n"
cp $(obj)/coreboot.pre $@.tmp
$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG)

10
src/cpu/samsung/exynos5250/Makefile.inc
View file

@ -1,8 +1,3 @@
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
INTERMEDIATE += exynos5250_add_bl1
bootblock-y += spi.c alternate_cbfs.c
bootblock-y += pinmux.c mct.c power.c
# Clock is required for UART
@ -54,6 +49,11 @@ ramstage-y += fb.c
ramstage-y += usb.c
ramstage-y += cbmem.c
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
.PHONY: exynos5250_add_bl1
$(obj)/coreboot.rom: exynos5250_add_bl1
exynos5250_add_bl1: $(obj)/coreboot.pre
printf " DD Adding Samsung Exynos5250 BL1\n"
dd if=3rdparty/cpu/samsung/exynos5250/bl1.bin \

10
src/cpu/samsung/exynos5420/Makefile.inc
View file

@ -1,8 +1,3 @@
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
INTERMEDIATE += exynos5420_add_bl1
bootblock-y += spi.c alternate_cbfs.c
bootblock-y += pinmux.c mct.c power.c
# Clock is required for UART
@ -60,6 +55,11 @@ rmodules-y += mct.c
VBOOT_STUB_DEPS += $(obj)/cpu/samsung/exynos5420/monotonic_timer.rmodules.o
VBOOT_STUB_DEPS += $(obj)/cpu/samsung/exynos5420/mct.rmodules.o
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
.PHONY: exynos5420_add_bl1
$(obj)/coreboot.rom: exynos5420_add_bl1
exynos5420_add_bl1: $(obj)/coreboot.pre
printf " DD Adding Samsung Exynos5420 BL1\n"
dd if=3rdparty/cpu/samsung/exynos5420/bl1.bin \