0c5f61a01c
When we first created the arm64 port, we weren't quite sure whether coreboot would always run in EL3 on all platforms. The AArch64 A.R.M. technically considers this exception level optional, but in practice all SoCs seem to support it. We have since accumulated a lot of code that already hardcodes an implicit or explicit assumption of executing in EL3 somewhere, so coreboot wouldn't work on a system that tries to enter it in EL1/2 right now anyway. However, some of our low level support libraries (in particular those for accessing architectural registers) still have provisions for running at different exception levels built-in, and often use switch statements over the current exception level to decide which register to access. This includes an unnecessarily large amount of code for what should be single-instruction operations and precludes further optimization via inlining. This patch removes any remaining code that dynamically depends on the current exception level and makes the assumption that coreboot executes at EL3 official. If this ever needs to change for a future platform, it would probably be cleaner to set the expected exception level in a Kconfig rather than always probing it at runtime. Change-Id: I1a9fb9b4227bd15a013080d1c7eabd48515fdb67 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
68 lines
1.6 KiB
C
68 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cache.h>
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#include <arch/lib_helpers.h>
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#include <arch/stages.h>
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#include <arch/transition.h>
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#include <arm_tf.h>
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#include <cbmem.h>
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#include <compiler.h>
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#include <console/console.h>
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#include <program_loading.h>
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#include <rules.h>
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#include <string.h>
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static void run_payload(struct prog *prog)
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{
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void (*doit)(void *);
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void *arg;
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doit = prog_entry(prog);
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arg = prog_entry_arg(prog);
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u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L);
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if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE))
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arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr);
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else
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transition_to_el2(doit, arg, payload_spsr);
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}
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void arch_prog_run(struct prog *prog)
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{
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void (*doit)(void *);
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void *arg;
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if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) {
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run_payload(prog);
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return;
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}
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doit = prog_entry(prog);
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arg = prog_entry_arg(prog);
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doit(prog_entry_arg(prog));
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}
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int arch_supports_bounce_buffer(void)
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{
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return 0;
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}
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/* Generic stage entry point. Can be overridden by board/SoC if needed. */
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__weak void stage_entry(void)
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{
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main();
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}
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